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30a, 100v the irsm005301mh is a general purpose halfbridge with integrated gate driver in an attractive 7x8mm pqfn package. it is a general purpose building bloc k suitable for a variety of low voltage application s where power density is of critical importance. typical ex amples would be advanced motor drives, dctoac and dc todc converters. ? package with low thermal resistance and minimal pa rasitics ? low onresistance hexfets: 16 m typ. ? undervoltage lockout on vcc and vbs ? independent gate drive in phase with logic input ? gate drive supply range from 10v to 20v ? propagation delay matched to defined spec ? 3.3v, 5v and 15v logic input compatible ? rohs compliant ! "#! "$ %& '& irsm005301mh pqfn 7x8mm tray 1300 irsm005301mhtr pqfn 7x8mm tape and reel 2000 ( " )*+ , downloaded from: http:///

,! - absolute maximum ratings indicate sustained limits beyond which damage to the module may occur. these are not tested at manufacturing. all voltage parameter s are absolute voltages referenced to v ss unless otherwise stated in the table. the thermal resistance rating is measured under board mounted and still air cond itions. &! - . ! ! " # !!! $
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&"# ! ) *% 5 6#21 #2"&&78 # ! . 9 6#21 #2"&&7 28 # 5! 59 . %% : 1$12"&&78 # ! . , : #&"8 #:,6, ! . %%9 . note1: calculated based on maximum junction tempera ture. bond wires current limit is 20a / 0 v bias (v cc , v bs )=15v, tj=25oc, unless otherwise specified. &! %& - . 0 v (br)dss draintosource breakdown voltage 100 v h in =l in =0v, i d =250a v gs(th) gate threshold voltage 2.0 3.0 4.0 v i d =100a 16 21 i d =10a, t j =25c r ds(on) draintosource voltage 35 m i d =10a, t j =150c 20 h in =l in =0v, v + =100v i dss zero gate voltage drain current 250 a h in =l in =0v, v + =100v, t j =125c 0.7 0.82 i f =10a v sd mosfet diode forward voltage drop 0.6 v i f =10a, t j =125c i gss gate to source leakage +/100 na v gs =+/20v rbsoa reverse bias safe operating area full square, limited by t jmax v + = 100v, v cc =+15v to 0v q g total gate charge 36 54 q gs gate to source charge 7 q gd gate to drain charge 11 nc i d =26a v ds = 20v v gs =10v eas single pulse avalanche energy 6.1 mj downloaded from: http:///

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0/ for proper operation the device should be used with in the recommended conditions. all voltages are abs olute referenced to com. the vs offset is tested with all supplies biased at 15v differential. for more deta ils, see irs2005 data sheet. &! %& - . v b high side floating supply voltage v s +10 v s +15 v s +20 v v s high side floating supply offset voltage note 1 100 v v cc low side and logic fixed supply voltage 10 15 20 v v in logic input voltage lin, hin com v cc v hin high side pwm pulse width 1 s deadtime suggested dead time between hin and lin 0. 3 0.5 s 0 / v bias (v cc , v bs )=15v, t j =25oc, unless otherwise specified. the v in , and i in parameters are referenced to com &! %& - . v in,th+ positive going input threshold for lin, hin 2.5 v v in,th negative going input threshold for lin, hin 0.8 v v bsuv+ v bs supply undervoltage, positive going threshold 8.0 8.9 9.8 v v bsuv v bs supply undervoltage, negative going threshold 7.4 8.2 9.0 v v bsuvh v bs supply undervoltage lockout hysteresis 0.8 v v ccuv+ v cc / supply undervoltage, positive going threshold 8.0 8.9 9.8 v v ccuv v cc supply undervoltage, negative going threshold 7.4 8.2 9.0 v v ccuvh v cc supply undervoltage lockout hysteresis 0.8 v i qbs quiescent v bs supply current 30 75 a i qcc quiescent v cc supply current 150 520 a i lk offset supply leakage current 50 a i o+ ic high output short circuit current 200 290 vo=0v vin=logic 1 pw<10us i o ic low output short circuit current 420 600 vo=15v vin=logic 0 pw<10us i in+ input bias current v in =5v for lin, hin 4 10 a i in input bias current v in =0v for lin, hin 0.5 1 a downloaded from: http:///

& 0 / v bias (v cc , v bs )=15v, tj=25oc, c l =1000pf unless otherwise specified. driver only tim ing unless otherwise specified. &! %& - . 0 t on input to output propagation turnon delay time (see fig.3) 160 220 ns t off input to output propagation turnoff delay time (see fig. 3) 150 220 ns t r input to output turnon rise time (see fig.3) 70 170 ns t f input to output turnoff fall time (see fig. 3) 35 95 ns mt delay matching, hs and ls turn on/off 50 ns % 0 &! %& - . 0 r th(jb) thermal resistance, junction to mounting pad, each mosfet 3.8 c/w standard reflowsolder process r th(ja) thermal resistance, junction to ambient, each mosfet 40 c/w mounted on 50mm 2 of fourlayer fr4 with 28 vias )) / %! 6, :, ;< 6 6 ! "# : : == 6 : 9 : 6 =9
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" " # 3, 6, 8 com low side gate driver return 2 v cc 15v gate drive supply 4 hin logic input for high side (active high) 5 lin logic input for low side (active high) 7 lo low side gate drive output 9 g2 low side fet gate 10, 16, 17 v s phase output 11 to 15 v low side source connection 18 to 23 v+ dc bus 24 g1 high side fet gate 25 ho high side gate drive output 26, 27 v s phase output (ve of bootstrap cap connection) 1 v b high side floating supply (+ve bootstrap cap connec tion) bottom of package view vb vcc com hin lin com lo 7 g2 9 vs v- 11 v- 12 v- 13 v- 14 16 vs v- 15 17 vs 18-v+ 19 20 v+ 21 v+ 22 v+ 23 v+ com 8 26 vs 24 g1 25 ho 27 vs v+ 10 1 2 3 4 5 6 $& 21&1+0-2 > 1 % >&
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figure 1: typical application connection 1. bus capacitors should be mounted as close to the module bus terminals as possible to reduce ringing and emi problems. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. 2. value of the bootstrap capacitors depends upon the switching frequency. their selection should be made based on ir design tip dt044 or application n ote an1044. figure 2. ic switching waveforms definitions. downloaded from: http:///

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' ' ) / industrial ?? (per jedec jesd 47e) /&) / msl3 ??? (per ipc/jedec jstd020c) machine model class a (200v) (per jedec standard jesd22a115a) human body model class 2 (2000v) (per eia/jedec standard eia/jes001a2011) 0 yes ? qualification standards can be found at internation al rectifiers web site hu http://www.irf.com/ u ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative f or further information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. downloaded from: http:///

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53 1. for mounting instruction see an1168. 2. for recommended pcb via design see an1091. 3. for recommended design, solder profile, integrat ion and rework guidelines see an1028. 4. for board inspection guidelines see an1133. downloaded from: http:///

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data and specifications are subject to change witho ut notice 6),'.,%7 233 kansas st., el segundo, california 90245, usa tel: (310) 2527105 tac fax: (310) 2527903 visit us at www.irf.com for sales contact informati on downloaded from: http:///

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